1. Field of the Invention
This invention relates generally to controllers for data transfer between peripheral storage devices and a host computer. In particular, the invention provides an architecture and method for interfacing multiple external peripheral devices to a dynamic random access memory buffer using an arbitrated priority access to the buffer for page mode transfer to and from the buffer.
2. Prior Art
Peripheral controllers for data storage units such as hard disks control communications between a host computer system and the data storage unit. Typically, the use of a buffer memory associated with the peripheral controller to accommodate the differing data transfer rates of the storage device and computer has been employed. Examples of such controllers are disclosed in U.S. Pat. No. 4,527,233 to Ambrosius III, et al. and in U.S. patent application Ser. No. 07/220,531 to Bonke, et al. for a DATA RECORDING SYSTEM BUFFER MANAGEMENT AND MULTIPLE HOST INTERFACE CONTROL, filed July 18, 1988.
The use of dynamic random access memories as the buffer in peripheral control devices is desirable due to their simplicity and cost effectiveness. However, typically, dynamic RAMs do not have random access bandwidth sufficient to sustain multiple high speed devices. This is partially due to the requirement for refreshing the memory to maintain data integrity. Many dynamic RAMs, however, do incorporate a feature known as "page mode or static column" which allows an increase in their bandwidth. To accommodate the page mode feature to obtain the higher bandwidth, the controller must be able to accommodate data transfers in a continuous block. Such "burst mode" transfers are compatible with the direct memory access (DMA) protocols currently in existence. However, the controller must provide a first-in-first-out (FIFO) subbuffer to handle data streaming from the external devices to the DRAM buffer. In addition, the controller must be able to arbitrate the simultaneous demands on the buffer for transfers to and from multiple external devices such as a host computer and disk drive, plus accommodate the refresh requirements of the DRAM.